1. Field of the Invention
The present invention generally relates to signal multiplexers and, more particularly, to a high speed multiplexer which minimizes signal delay and produces no loss of signal levels. The multiplexer according to the invention has particular application in high speed logic and memory circuits which incorporate scan test inputs requiring good isolation between system data and test data inputs.
2. Description of the Prior Art
A multiplexer is an electronic switch that connects one of two or more signal sources to a load. In one particular application, a multiplexer is used in a logic or memory chip that requires its receiving circuits to accept either system data inputs or test data inputs. Although the multiplexer function for this application can be easily performed using conventional logic circuits, the delay introduced into the system data paths would be intolerable for high performance logic and memory chips. What is needed for these high performance chips is a multiplexer circuit which, in the system mode, introduces a minimal delay in the system data paths and provides good isolation between system data inputs and test data inputs. The multiplexer circuit should be a high performance circuit, matching the performance of the logic and memory circuits of the chips in which they are incorporated, and preferably insure no signal loss between input and output terminals.